Data Path Allocation Techniques for High-level Synthesis of Low BIST Area Overhead Designs

Built-in self-test (BIST) techniques have evolved as cost-eeective techniques for testing digital circuits. These techniques add test circuitry to the chip such that the chip has the capability to test itself. A prime concern in using BIST is the area overhead due to the modiication of normal registers to BIST registers. This paper proposes a high-level synthesis methodology that addresses this concern at an early stage in the design cycle. Data path allocation algorithms are presented that 1) maximize the sharing of registers as BIST resources resulting in a small number of registers being modiied for BIST, and 2) minimize the number of CBILBO registers required in the BIST version. The designs synthesized by our algorithms have the same number of functional modules and registers as those synthesized using traditional approaches but with a much lower testability overhead.